1. Field of the Invention
The present invention relates to integrated circuit designs. In particular, the present invention relates to the design of a distribution system for clock signals in an integrated circuit.
2. Discussion of the Related Art
"Clock skew" is a measure of uncertainty in the arrival times of a clock signal transition at different locations of a synchronous logic circuit, such as a microprocessor. Clock skews are undesirable since they adversely impact the operating frequency attainable by the logic circuit. Consequently, clock skews should be minimized. Clock skew can arise, for example, from RC delays in the interconnect wires between circuit elements, mismatches in the capacitive loads presented to clock buffers, and mismatches of driver sizes in clock buffers distributing the clock signals.
In the prior art, the clock distribution system (i.e. the placement of clock buffers and the routing of clock signals) in a full-custom microprocessor is often hand-crafted to minimize clock skew. Clearly, such procedure is time-consuming.
As the complexity of microprocessors grows, microprocessor designs have become "semi-custom". In a semi-custom design, building blocks such as macros (e.g. regularly placed memory cells), arrayed logic elements (e.g. elements in data paths and register files) and standard cells (e.g. "random" logic) are used. Such building blocks are typically developed with automatic tools, such as logic synthesis, automatic placement and routing tools, which render the design task highly automated and efficient. However, as the design tasks are automated, hand-crafting the clock distribution system has become highly complex and impractical.
Clock distribution in a semi-custom design must take into account the nature of the various building blocks in the circuit. For example, within a custom macro block, the designer can still carefully place each transistor, route the wires for the clock signals and, where necessary, provide careful buffering of clock signals. In such a design, the designer can specify a "zero-skew" point, which is typically an entry point of the clock signal into the macro. Because the designer maintains control over placement and routing of the clock signals, clock skews within a custom macro block can usually be controlled by design decisions.
Arrayed logic elements, which are highly regular and with planned wiring locations built-in, allow a disciplined clock signal distribution strategy, as the total clock loading for the array and appropriate placements of clock buffers can be fairly accurately determined. Often, however, such arrayed logic element are placed and routed by automated tools. Such tools must be carefully directed to achieve the desired routing of clock signals.
Logic circuits built from standard cells belong to the most difficult class of circuits to route clock signals. Standard cell designs are primarily generated using a logic synthesis tool. In such a design, the designer provides the logic synthesis tool with a set of logic equations which express the desired logic circuit functionally. The synthesis tool then generates the implementation of the logic circuit, selecting circuit elements (e.g. logic gates) from a standard cell library. Various optimization techniques are typically applied to achieve such objectives as high cell density and gate minimization. Thus, the designer usually has no accurate means for predicting the sizes and locations of the capacitive loads driven by the clock signals, so that the number of clock buffers needed to adequately drive these capacitive loads and their optimal placements are not known in advance. Further, even for minor modification of the circuit, the logic synthesis tool often generates a radically different circuit topology for the circuit, such that a different clock distribution network may be required with each modification.
Because macros, arrayed logic and standard cells can often all be found in a semi-custom circuit, such as a microprocessor integrated circuit, it is desirable to have an automatic design tool which takes into account the different natures of these building blocks in placing clock buffers and routing clock signals, so as to achieve minimal clock skew in the integrated circuit.